
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:50:54 03/04/2012
-- Design Name:   Alu
-- Module Name:   C:/Xilinx92i/PROJECTAIC/tb_Alu.vhd
-- Project Name:  Procesador
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Alu
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- FAILUREs: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_Alu_vhd IS
END tb_Alu_vhd;

ARCHITECTURE behavior OF tb_Alu_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT Alu
	PORT(
		r1 : IN std_logic_vector(7 downto 0);
		r2 : IN std_logic_vector(7 downto 0);
		inm : IN std_logic_vector(7 downto 0);
		mux8_sel : IN std_logic;
		alu_op : IN std_logic_vector(3 downto 0);
		alu_ext : IN std_logic_vector(2 downto 0);
		int_ZF : IN std_logic;
		int_CF : IN std_logic;
		interrupt_read : IN std_logic;
		clk : in  STD_LOGIC;		
		ZF : OUT std_logic;
		CF : OUT std_logic;
		alu_o : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL mux8_sel :  std_logic := '0';
	SIGNAL int_ZF :  std_logic := '0';
	SIGNAL int_CF :  std_logic := '0';
	SIGNAL interrupt_read :  std_logic := '0';
	SIGNAL r1 :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL r2 :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL inm :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL alu_op :  std_logic_vector(3 downto 0) := (others=>'0');
	SIGNAL alu_ext :  std_logic_vector(2 downto 0) := (others=>'0');
	SIGNAL clk : STD_LOGIC := '1';	

	--Outputs
	SIGNAL ZF :  std_logic;
	SIGNAL CF :  std_logic;
	SIGNAL alu_o :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: Alu PORT MAP(
		r1 => r1,
		r2 => r2,
		inm => inm,
		mux8_sel => mux8_sel,
		alu_op => alu_op,
		alu_ext => alu_ext,
		int_ZF => int_ZF,
		int_CF => int_CF,
		ZF => ZF,
		CF => CF,
		clk => clk,
		interrupt_read => interrupt_read,
		alu_o => alu_o
	);


	clk <= not clk after 25 ns; -- 50 ns de periodo

	tb : PROCESS
	BEGIN

			
			
--			assert (1 /= 1)
--			report "peto2"
--			severity FAILURE;
			

		-- Wait 100 ns for global reset to finish
		--wait for 40 ns;
			
			
		--aritmeticas y logicas sin inmediato
			mux8_sel <= '0'; --sin inmediato
			
			
			--suma								
					r1 <= "10101010";
					r2 <= "01010101";
					alu_op <= "1110";			
					alu_ext <= "000";
					wait for 50 ns;
					assert(alu_o = "11111111")
						report "ERROR en suma"
						severity FAILURE;
					
					
					
			--suma con carry
					r1 <= "00000001";
					r2 <= "00000000";
					int_CF <= '1';
					alu_op <= "1110";
					alu_ext <= "001";										
					wait for 50 ns;
					assert(alu_o = "00000010")
						report "ERROR en suma con carry"
						severity FAILURE;
					
					

					
			--resta			
					r1 <= "00000111";
					r2 <= "00000001";
					alu_op <= "1110";
					alu_ext <= "010";
					wait for 50 ns;
					assert(alu_o = "00000110")
						report "ERROR en resta"
						severity FAILURE;
					

					
					
			--resta con carry
					r1 <= "11111111";
					r2 <= "00000000";
					int_CF <= '1';
					alu_op <= "1110";
					alu_ext <= "011";			
					wait for 50 ns;
					assert(alu_o = "11111110")
						report "ERROR en resta con carry"
						severity FAILURE;
					
					
					
		--logicas
			--and			
					r1 <= "11100111";
					r2 <= "01011010";
					alu_op <= "1110";
					alu_ext <= "100";
					wait for 50 ns;--290ns
					assert(alu_o = "01000010")
						report "ERROR en and"
						severity FAILURE;
										
															
			--or
					r1 <= "11110000";
					r2 <= "00001111";					
					alu_op <= "1110";
					alu_ext <= "101";
					wait for 50 ns;--340ns
					assert(alu_o = "11111111")
						report "ERROR en or"
						severity FAILURE;

																	
			--xor
			
					r1 <= "10101010";
					r2 <= "10101010";
					alu_op <= "1110";
					alu_ext <= "110";
					wait for 50 ns;--390ns
					assert(alu_o = "00000000")
						report "ERROR en xor"
						severity FAILURE;
					
						
		--inmediato
			mux8_sel <= '1'; --con inmediato
								
			--suma								
					r1 <= "10101010";
					inm <= "01010101";
					alu_op <= "1110";			
					alu_ext <= "000";
					wait for 50 ns;--440ns
					assert(alu_o = "11111111")
						report "ERROR en suma con inmediato"
						severity FAILURE;
										
			--suma con carry
					r1 <= "00000001";
					inm <= "00000000";
					int_CF <= '1';
					alu_op <= "1110";
					alu_ext <= "001";
					wait for 50 ns;--490ns
					assert(alu_o = "00000010")
						report "ERROR en suma con inmediato con carry"
						severity FAILURE;
										
				
										
			--resta			
					r1 <= "11110000";
					inm <= "11110000";
					alu_op <= "1110";
					alu_ext <= "010";
					wait for 50 ns;--540ns
					assert(alu_o = "00000000")
						report "ERROR en resta con inmediato"
						severity FAILURE;
					
			--resta con carry
					r1 <= "11111111";
					inm <= "00000000";
					int_CF <= '1';
					alu_op <= "1110";
					alu_ext <= "011";					
					wait for 50 ns;--590ns
					assert(alu_o = "11111110")
						report "ERROR en resta con inmediato con carry"
						severity FAILURE;
					
					
			
		--logicas con inmediato
					
			--and			
					r1 <= "11100111";
					inm <="01011010";
					alu_op <= "1110";
					alu_ext <= "100";
					wait for 50 ns;--640ns
					assert(alu_o = "01000010")
						report "ERROR en and con inmediato"
						severity FAILURE;
									
															
										
			--or
					r1 <= "11110000";
					inm <= "00001111";					
					alu_op <= "1110";
					alu_ext <= "101";
					wait for 50 ns;--690ns
					assert(alu_o = "11111111")
						report "ERROR en or con inmediato"
						severity FAILURE;
									
			--xor			
					r1 <= "10101010";
					inm <= "10101010";
					alu_op <= "1110";
					alu_ext <= "110";
					wait for 50 ns;--740ns
					assert(alu_o = "00000000")
						report "ERROR en xor con inmediato"
						severity FAILURE;
					
		
		--desplazamiento y rotacion
				mux8_sel <= '0'; --con inmediato
				
			--sll
				r2 <= "001" & "00000";
				r1 <= "10101010";			
				
				alu_op <= "1100";
				alu_ext <= "000";
				wait for 50 ns;--790ns
				assert (alu_o = "01010100")
					report "ERROR en sll"
					severity FAILURE;
									
			--srl
				r2 <= "001" & "00000";
				r1 <= "10101010";
				alu_op <= "1100";
				alu_ext <= "001";
				wait for 50 ns;--840ns
				assert(alu_o = "01010101")
						report "ERROR en srl"
						severity FAILURE;
									
					
									
			--sla
				r1 <= "00010111";
				r2 <= "001" & "00000";					
				alu_op <= "1100";
				alu_ext <= "010";	
				wait for 50 ns;--890ns
				assert(alu_o = "00101110")
						report "ERROR en sla"
						severity FAILURE;
				
			--sra
				r2 <= "001" & "00000";
				r1 <= "00101010";				
				alu_op <= "1100";
				alu_ext <= "011";				
				wait for 50 ns;--940ns
				assert(alu_o = "00101010")
						report "ERROR en sra"
						severity FAILURE;
			
					
					
			--rol
				r2 <= "001" & "00000";
				r1 <= "10101010";
				alu_op <= "1100";
				alu_ext <= "100";				
				wait for 50 ns;--990ns
				assert(alu_o = "01010101")
						report "ERROR en rol"
						severity FAILURE;
									
							
					
					
			--ror
				r2 <= "001"  & "00000";
				r1 <= "10101010";
				alu_op <= "1100";
				alu_ext <= "101";				
				wait for 50 ns;--1040ns
				assert(alu_o = "01010101")
						report "ERROR en ror"
						severity FAILURE;
									
				
				
		-- Place stimulus here
		 --wait for 50 ns;
		 report ("**********TESTS DE ALU SUPERADOS**********")
		 severity NOTE;
		wait; -- will wait forever
	END PROCESS;

END;
